ABSTRACTS OF ARTICLES OF THE JOURNAL "INFORMATION TECHNOLOGIES".
No. 4. Vol. 27. 2021

DOI: 10.17587/it.27.171-179

P. A. Lyakhov, PhD of Physics and Mathematics Sciences, Assistant Professor, Department of Applied Mathematics and Mathematical Modeling, e-mail: ljahov@mail.ru, A. S. Ionisyan, PhD of Physics and Mathematics Sciences, Assistant Professor, Department of Applied Mathematics and Mathematical Modeling, e-mail: asion@mail.ru, M. V. Valueva, PhD student, e-mail: mriya.valueva@mail.ru, A. S. Larikova, PhD student, e-mail: larikova@gmail.com, North-Caucasus Federal University, Stavropol, 357736, Russian Federation

High Performance Digital Filtering on Modified Multiply and Accumulate Unit in Residue Number System with Special Type of Moduli

The paper proposes the implementation of digital filtering using residue number system and the modified truncated multiply and accumulate unit. The work was carried out a theoretical analysis of digital filters using residue number system arithmetic and implemented hardware simulation on FPGA. FPGA hardware simulation results show that the use of residue number system allows to increase the frequency of digital filters up to about 4 times and hardware costs reduce up to 3 times compared to using a common positional number system. The obtained results open up the possibility for efficient hardware implementation of digital filters on modern devices (FPGA, ASIC and etc.) to solve practical problems, such as noise reduction, amplification and suppression of the frequency spectrum, interpolation, decimation, equalization and many others.
Keywords: digital signal processing, digital filter, multiply and accumulate unit, residue number system

P. 171–179

Acknowledgments: This work was supported by the Russian Federation for Basic Research (projects no. 19-07-00130A) and by the Presidential Grant of the Russian Federation (projects no. SP-126.2019.5 and no. MK-3918.2021.1.6).

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