main| new issue| archive| editorial board| for the authors| publishing house|
Ðóññêèé
Main page
New issue
Archive of articles
Editorial board
For the authors
Publishing house

 

 


ABSTRACTS OF ARTICLES OF THE JOURNAL "INFORMATION TECHNOLOGIES".
No. 1. Vol. 31. 2025

DOI: 10.17587/it.31.3-15

D. V. Efanov, D. Sc., Professor,
Peter the Great St. Petersburg Polytechnic University, St. Petersburg, 195251, Russian Federation, Russian University of Transport, Moscow, 127994, Russian Federation, Tashkent State Transport University, Tashkent, 100167, Uzbekistan, Scientific Research and Design Institute "Transport and Construction Safety" LLC, St. Petersburg, 192102, Russian Federation,
Y. I. Yelina, Ph. D. Student,
Peter the Great St. Petersburg Polytechnic University, St. Petersburg, 195251, Russian Federation

Accounting the Ways of Weighing the Bits of the Data Vector when Constructing a Code with Summation in the Ring of Deductions Modulo M = 4 in the Synthesis of Self-Checking Discrete Devices Based on Boolean Signals Correction

The article shows that in the synthesis of concurrent error-detection circuit based on Boolean signals correction, weighted codes with summation in the ring of deductions modulo M = 4 (weight-based Bose — Lin codes) with various arrays of weighting coefficients can be effectively used. The codes with four data and two test symbols used in organizing the control of calculations in a group of six outputs of the diagnostic object are considered in more detail. Four arrays of weight coefficients are highlighted: [1, 1, 1, 2], [1, 1, 2, 3], [1, 2, 2, 3], [2, 2, 2, 3] — the use of which in the construction of a weight-based Bose — Lin code leads to the formation of for each the test vector has exactly one data vector of the following types: <00ab>, <01 ab>, <10ab>, <11 ab>, where a, b ' {0, 1}. This property allows the use of codes with the specified arrays of weighting coefficients in the synthesis of concurrent error-detection circuit with the conversion of only part of the signals from the diagnostic object — two signals involved in the formation of the lower bits of the data vector. The article presents the results of experimental studies of weight-based Bose — Lin codes in the synthesis of concurrent error-detection circuit based on the Boolean signals correction using two algorithms. The first algorithm is based on the use of converting only those signals from the diagnostic object that are involved in the formation of test symbols. The second algorithm is based on the conversion of only those signals from the diagnostic object that participate in the formation of the two lowest digits of the data vector. It has been experimentally established that self-checking devices synthesized using a code with an array of weighting coefficients have the highest efficiency in terms of structural redundancy [2, 2, 2, 3] (on average, the value of the structural redundancy index has been reached at 73 % of the duplication structure). Next, according to this indicator, there are devices synthesized using a code with an array of weighting coefficients [1, 2, 2, 3] (on average, 76—77 % of the duplication structure). The use of arrays of weighting coefficients [1, 1, 2, 3] and [1, 1, 1, 2] in the construction of the code gives a slightly lower effect (on average 79—81 % from the duplication structure). It is shown that in order to ensure complete self-checking of device structures, it will be necessary to use permutations of outputs within controlled groups of outputs of the initial diagnostic object and between groups. The results of the study can be taken into account when developing self-checking digital devices, as well as software tools for their computer-aided design.
Keywords: self-checking structures; Boolean signals correction; concurrent error-detection circuit; weight-based Bose-Lin code; structural redundancy of self-checking devices; ensuring self—verification

P. 3-15

References

  1. Soghomonyan E. S., Slabakov E. V. Self-checking devices and fault-tolerant systems, Moscow, Radio and communications, 1989, 208 p. (in Russian).
  2. Mikoni S. V. General diagnostic knowledge bases of computing systems, St. Petersburg, SPIIRAN, 1992, 234 p. (in Russian).
  3. Gavzov D. V., Sapozhnikov V. V., Sapozhnikov Vl. V. Methods of ensuring the safety of discrete systems, Automation and telemechanics, 1994, no. 8, pp. 3—50 (in Russian).
  4. Lala P. K. Self-Checking and Fault-Tolerant Digital Design, San Francisco, Morgan Kaufmann Publishers, 2001, 216 p.
  5. Drozd A. V., Kharchenko V. S., Antoshchuk S. G., Drozd Yu. V., Drozd M. A., Sulima Yu. Y. Operational diagnostics of secure data management systems, Edited by A. V. Drozda and V. S. Kharchenko, Kharkiv, National Aerospace University named after N. E. Zhukovsky "KHAI", 2012, 614 p. (in Russian).
  6. Kharchenko V., Kondratenko Yu., Kacprzyk J. Green IT Engineering: Concepts, Models, Complex Systems Architectures, Springer Book series "Studies in Systems, Decision and Control", 2017, vol. 74, p. 305, doi: 10.1007/978-3-319-44162-7.
  7. Mikoni S. Top Level Diagnostic Models of Complex Objects, Lecture Notes in Networks and Systems, 2022, vol. 442, pp. 238—249, doi: 10.1007/978-3-030-98832-6_21.
  8. Nicolaidis M., Zorian Y. On-Line Testing for VLSI — À Compendium of Approaches, Journal of Electronic Testing: Theory and Applications, 1998, no. 12, pp. 7—20, doi: 10.1023/A: 1008244815697.
  9. Mitra S., McCluskey E. J. Which Concurrent Error Detection Scheme to dioose, Proceedings of International Test Conference, 2000, USA, Atlantic City, NJ, 03-05 October 2000, pp. 985—994, doi: 10.1109/TEST.2000.894311.
  10. Sapozhnikov V. V., Sapozhnikov Vl. V. Self-checking discrete devices, St. Petersburg, Energoatomizdat, 1992, 224 p. (in Russian).
  11. Piestrak S. J. Design of Self-Testing Checkers for Unidirectional Error Detecting Codes, Wroclaw, Oficyna Wydawnicza Politechniki Wroclavskiej, 1995, 111 p.
  12. Sapozhnikov V. V., Sapozhnikov Vl. V., Efanov D. V. Summation codes for technical diagnostics systems. Vol. 1: Classical Berger Codes and their modifications, Moscow, Nauka, 2020, 383 p. (in Russian).
  13. Sapozhnikov V. V., Sapozhnikov Vl. V., Efanov D. V. Summation codes for technical diagnostics systems. Vol. 2: Weight-based sum codes, Moscow, Nauka, 2021, 455 p. (in Russian).
  14. Gessel M., Morozov A. V., Sapozhnikov V. V., Sapozhnikov Vl. V. Control of combinational circuits by the method of logical addition, Automation and telemechanics, 2005, no. 8, pp. 161—172 (in Russian).
  15. Goessel M., Morozov A. V., Sapozhnikov V. V., Sapozhnikov Vl. V. Logical addition — a new method of control of combinational circuits, Automation and telemechanics, 2003, no. 1, pp. 167—176 (in Russian).
  16. Goessel M., Ocheretny V., Sogomonyan E., Marienfeld D. New Methods of Concurrent Checking: Edition 1, Dordrecht, Springer Science + Business Media B. V., 2008, 184 p.
  17. Sen S. K. A Self-Checking Circuit for Concurrent Checking by 1-out-of-4 code with Design Optimization using Constraint Don't Cares, National Conference on Emerging trends and advances in Electrical Engineering and Renewable Energy (NCEEERE 2010), Sikkim Manipal Institute of Technology, Sikkim, held during 22—24 December, 2010.
  18. Das D. K., Roy S. S., Dmitiriev A., Morozov A., Gossel M. Constraint Don't Cares for Optimizing Designs for Concurrent Checking by 1-out-of-3 Codes, Proceedings of the 10tH International Workshops on Boolean Problems, Freiberg, Germany, September, 2012, pp. 33—40.
  19. Pivovarov D. V. Construction of functional check systems for multi-output combinational circuits by the method of logical addition according to equilibrium codes, Automation in transport, 2018, vol. 4, no. 1, pp. 131—149 (in Russian).
  20. Efanov D. V., Sapozhnikov V. V., Sapozhnikov Vl. V., Pivovarov D. V. The Synthesis Conditions of Completely Self-Testing Embedded-Control Circuits Based on the Boolean Comple­ment Method to the "1-out-of-m" Constant-Weight Code, Automatic Control and Computer Sciences, 2020, vol. 54, iss. 2, pp. 89—99, doi: 10.3103/S0146411620020042.
  21. Morozov M., Saposhnikov V. V., Saposhnikov Vl. V., Goessel M. New Self-Checking Circuits by Use of Berger-codes, Proceedings of 6th IEEE International On-Line Testing Workshop, Palma De Mallorca, Spain, 3—5 July 2000, pp. 171—176.
  22. Berger J. M. A Note on Error Detection Codes for Asymmetric Channels, Information and Control, 1961, vol. 4, iss. 1, pp. 68—73, doi: 10.1016/S0019-9958(61)80037-5.
  23. Efanov D. V., Sapozhnikov V. V., Sapozhnikov Vl. V. The Self-Checking Concurrent Error-Detection Systems Synthesis Based on the Boolean Complement to the Bose-Lin Codes with the Modulo Value M = 4, Electronic Modeling, 2021, vol. 43, iss. 1, pp. 28—45, doi: 10.15407/emodel.43.01.028.
  24. Slabakov E. V. Construction of fully self-verifiable combination devices using residual codes, Automation and telemechanics, 1979, no. 10, pp. 133—141 (in Russian).
  25. Das D., Touba N. A. Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes, Proceedings of 16th IEEE VLSI Test Symposium (Cat. No.98TB100231), 30 April 1998, Monterey, CA, USA, pp. 309—315, doi: 10.1109/ VTEST.1998.670885.
  26. Das D., Touba N. A. Synthesis of Circuits with Low-Cost Concurrent Error Detection Based on Bose-Lin Codes, Journal of Electronic Testing: Theory and Applications, 1999, vol. 15, iss. 1—2, pp. 145—155, doi: 10.1023/A:1008344603814.
  27. Efanov D. V., Sapozhnikov V. V., Sapozhnikov Vl. V. Application of modular codes with summation for building functional control systems of combinational logic circuits, Automation and telemechanics, 2015, no. 10, pp. 152—169.
  28. Efanov D. V., Pivovarov D. V., Osadchy G. V., Zueva M. V. Application of codes with effective error detection in the field of small multiplicity in the synthesis of Boolean signals correction using the logical complement method, Information Technologies, 2022, vol. 28, no. 6, pp. 283—293, doi: 10.17587/it.28.283-293 (in Russian).
  29. Berger J. M. A Note on Burst Detection Sum Codes, Information and Control, 1961, vol. 4, iss. 2—3, pp. 297—299, doi: 10.1016/S0019-9958(61)80024-7.
  30. Das D., Touba N. A. Weight-Based Codes and Their Application to Concurrent Error Detection of Multilevel Circuits, Proceedings of 17th IEEE Test Symposium, California, USA, 1999, pp. 370—376, doi: 10.1109/VTEST.1999.766691.
  31. Das D., Touba N. A., Seuring M., Gossel M. Low Cost Concurrent Error Detection Based on Modulo Weight-Based Codes, Proceedings of the IEEE 6th International On-Line Testing Workshop (IOLTW), Spain, Palma de Mallorca, July 3—5, 2000, pp. 171—176, doi: 10.1109/OLT.2000.856633.
  32. Mekhov V. B., Sapozhnikov V. V., Sapozhnikov V. V. Control of combinational circuits based on modified codes with summation, Automation and telemechanics, 2008, no. 8, pp. 153—165 (in Russian).
  33. Efanov D. V., Sapozhnikov V. V., Sapozhnikov V. V. Modified codes with summation of weighted discharges and transitions for solving problems of synthesis of discrete devices with fault detection, Electronic modeling, 2019, vol. 41, no. 2, pp. 39—61, doi: 10.15407/emodel.41.02.039 (in Russian).
  34. Efanov D. V., Yelina Y. I. Research of algorithms for the synthesis of self—checking digital devices based on Boolean sig­nals correction using weight-based Bose — Lin codes, Automation in transport, 2024, vol. 10, no. 1, pp. 74—99, doi: 10.20296/2412­9186-2024-10-01-74-99 (in Russian).
  35. McElvain K. IWLS'93 Benchmark Set: Version 4.0, Distributed as a part of IWLS'93 benchmark set, May 1993.
  36. Collection of Digital Design Benchmarks, available at: https://ddd.fit.cvut.cz/www/prj/Benchmarks/
  37. Sentovich E. M., Singh K. J., Moon C., Savoj H., Brayton R. K., Sangiovanni-Vincentelli A. Sequential Circuit Design Using Synthesis and Optimization, Proceedings IEEE International Conference on Computer Design: VLSI in Computers & Processors, 11—14 October 1992, Cambridge, MA, USA, pp. 328—333, doi: 10.1109/ICCD.1992.276282.
  38. Sentovich E. M., Singh K. J., Lavagno L., Moon C., Murgai R., Saldanha A., Savoj H., Stephan P. R., Brayton R. K., Sangiovanni-Vincentelli A. SIS: A System for Sequential Circuit Synthesis, Electronics Research Laboratory, Department of Electrical Engineering and Computer Science, University of California, Berkeley, 4 May 1992, 45 p.
  39. Aksenova G. P. Necessary and sufficient conditions for the construction of fully verifiable convolution schemes modulo 2, Automation and telemechanics, 1979, no. 9, pp. 126—135 (in Russian).
  40. Dhar K. Design of a Low Power, High Speed and Energy Efficient 3 Transistor XOR Gate in 45nm Technology Using the Conception of MVT Methodology, 2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT), 10—11 July 2014, Kanyakumari, India,doi: 10.1109/ICCICCT.2014.6992931.

 

To the contents