ABSTRACTS OF ARTICLES OF THE JOURNAL "INFORMATION TECHNOLOGIES".
No. 10. Vol. 29. 2023

DOI: 10.17587/it.29.503-511

D. V. Efanov, Dr. Sc., Professor,
Peter the Great St. Petersburg Polytechnic University, St. Petersburg, Russian University of Transport, Moscow, Tashkent State Transport University, Tashkent, Scientific Research and Design Institute "Transport and Construction Safety" LLC, St. Petersburg

Self-Checking Combinational Devices Synthesis Based on the Boolean Signal Correction Method Using Bose—Lin Codes

An organizing concurrent error-detection (CED) circuit new method for automation and computer technology combinational device is considered. The method based on the signal's Boolean correction method. The author proposed to use separable codes in the CED circuit synthesis when converting values from all operational outputs of the diagnosing object. The proposed approach allows to consider many possible transformations for each input combination. In addition, it will allow to choose the transformations to provide the conditions for building a completely self-checking device. In comparison with the methods previously discussed in the literature, the proposed approach makes it possible to synthesize a large number of control logic devices in the CED circuit and choose the most appropriate option. For example, with the technical implementation complexity lowest indicators. An algorithm for synthesizing the control logic block is given on the example of using a separable Bose — Lin code with module M = 4 by the signals Boolean correction method when organizing an CED circuit. The proposed method advantages and disadvantages for the CED circuit synthesis are described.

P. 503-511

References

1. Reynolds D. A., Meize G. Fault Detection Capabilities of Alternating Logic, IEEE Transactions on Computers, 1978, vol. c-27, iss. 12, pp. 1093—1098.
2. Aksjonova G. P. Restoration in Duplicated Units by the Method of Data Inversion, Avtomatika i Telemehanika, 1987, no. 10, pp. 144—153 (in Russian).
3. Shcherbakov N. S. Reliability of Work of Digital Devices, Moscow, Mashinostroenie, 1989, 224 p.
4. Sogomonyan E. S., Slabakov E. V. Self-Checking Devices and Fault-Toletant Systems, Moscow, Radio and communication, 1989, 208 p. (in Russian).
5. Fujiwara E. Code Design for Dependable Systems: Theory and Practical Applications, John Wiley & Sons, 2006, 720 p.
6. Goessel M., Graf S. Error Detection Circuits, London: McGraw-Hill, 1994, 261 p.
7. Sapozhnikov V. V., Sapozhnikov Vl. V., Efanov D. V. Theory of Synthesis of Self-Checking Digital Systems Based on Sum Codes, St. Petersburg, Lan', 2021, 580 p.
8. 18. Sapozhnikov V. V., Sapozhnikov Vl. V., Dmitriev A. V., Morozov A. V., Goessel M. Organization of Functional Control of Combinational Circuits by the Logic Complement Method, Electronic modeling, 2002, vol. 24, iss. 6, pp. 52—66 (in Russian).
9. 9. Goessel M., Morozov A. V., Sapozhnikov V. V., Sapozhnikov Vl. V. Logic Complement, a New Method of Checking the Combinational Circuits, Avtomatika i Telemehanika, 2003, no. 1, pp. 167—176 (in Russian).
10. Goessel M., Morozov A. V., Sapozhnikov V. V., Sapozhnikov Vl. V. Checking Combinational Circuits by the Method of Logic Complement, Avtomatika i Telemehanika, 2005, no. 8, pp. 161—172 (in Russian).
11. Saposhnikov Vl. V., Dmitriev A., Goessel M., Saposhnikov V. V. Self-Dual Parity Checking — a New Method for on Line Testing, Proceedings of 14th IEEE VLSI Test Symposium, USA, Princeton, 1996, pp. 162—168.
12. Aksjonova G. P. Method of Synthesizing Built-In Monitoring Arrangements for Automata with Memory, Avtomatika i Telemehanika, 1973, iss. 2, pp. 109—116 (In Russian).
13. Goessel M., Dmitriev A. V., Sapozhnikov V. V., Sapozhnikov Vl. V. A Functional Fault-Detection Self-Test for Combinational Circuits, Avtomatika i Telemehanika, 1999, no. 11, pp. 162—174 (In Russian).
14. Goessel M., Dmitriev A. V., Sapozhnikov V. V., Sapozhnikov Vl. V. Detection of Faults in Combinational Circuits by a Self-Dual Test, Avtomatika i Telemehanika, 2000, iss. 7, pp. 140—149 (In Russian).
15. Sapozhnikov V. V., Sapozhnikov Vl. V., Goessel M. Self-Dual Discrete Devices, St. Petersburg, Energoatomizdat (St. Petersburg branch), 2001, 331 p. (In Russian).
16. 16. Goessel M., Ocheretny V., Sogomonyan E., Marienfeld D. New Methods of Concurrent Checking: Edition 1, Dordrecht, Springer Science + Business Media B. V., 2008, 184 p.
17. Sen S. K. A Self-Checking Circuit for Concurrent Checking by 1-out-of-4 code with Design Optimization using Constraint Don't Cares, National Conference on Emerging trends and advances in Electrical Engineering and Renewable Energy (NCEEERE 2010), Sikkim Manipal Institute of Technology, Sikkim, held during 22—24 December, 2010.
18. Das D. K., Roy S. S., Dmitiriev A., Morozov A., Gossel M. Constraint Don't Cares for Optimizing Designs for Concurrent Checking by 1-out-of-3 Codes, Proceedings of the 10th International Workshops on Boolean Problems, Freiberg, Germany, September, 2012, pp. 33—40.
19. Sapozhnikov V. V., Sapozhnikov Vl. V Efanov D. V. Design of Self-Checking Concurrent Error Detection Systems Based on "2-out-of-4" Constant-Weight Code, Problemy Upravlenija, 2017, iss. 1, pp. 57—64 (In Russian).
20. Pivovarov D. V. Formation of Concurrent Error Detection Systems in Multiple-Output Combinational Circuits Using the Boolean Complement Method Based on Constant-Weight Codes, Avtomatika na Transporte, 2018, vol. 4, iss. 1, pp. 131—149 (In Russian).
21. Efanov D., Sapozhnikov V., Sapozhnikov Vl., Osadchy G., Pivovarov D. Self-Dual Complement Method up to Constant-Weight Codes for Arrangement of Combinational Logical Circuits Concurrent Error-Detection Systems, Proceedings of 17th IEEE East-West Design & Test Symposium (EWDTS'2019), Batumi, Georgia, September 13—16, 2019, pp. 136—143, DOI: 10.1109/EWDTS.2019.8884398.
22. Efanov D. V., Pivovarov D. V. The Hybrid Structure of a Self-Dual Built-In Control Circuit for Combinational Devices with Pre-Compression of Signals and Checking of Calculations by Two Diagnostic Parameters, Proceedings of 19th IEEE East-West Design & Test Symposium (EWDTS'2021), Batumi, Georgia, September 10—13, 2021, pp. 200—206, DOI: 10.1109/ EWDTS52692.2021.9581019.
23. Morozov M., Saposhnikov V. V., Saposhnikov Vl. V., Goessel M. New Self-Checking Circuits by Use of Berger-Codes, Proceedings of 6th IEEE International On-Line Testing Workshop, Palma de Mallorca, Spain, 3—5 July 2000, pp. 171—176.
24. Efanov D. V., Sapozhnikov V. V., Sapozhnikov Vl. V. The Self-Checking Concurrent Error-Detection Systems Synthesis Based on the Boolean Complement to the Bose-Lin Codes with the Modulo Value M = 4, Electronic Modeling, 2021, vol. 43, iss. 1, pp. 28—45, DOI: 10.15407/emodel.43.01.028.
25. Efanov D. V., Pogodina T. S. Check of Combinational Devices by Belonging of Calculated Functions to Self-Dual Class with Using Signal Compression Circuit Based on Linear Codes, Programmnaya Ingeneria, 2023, vol. 14, iss. 4, pp. 175—186, DOI: 10.17587/prin.14.4.175-186. (in Russian)
26. Efanov D., Osadchy G., Zueva M. Specifics of Error Detection with Modular Sum Codes in Concurrent Error-Detection Circuits Based on Boolean Complement Method, Proceedings of 19th IEEE East-West Design & Test Symposium (EWDTS'2021), Batumi, Georgia, September 10-13, 2021, pp. 59—69, DOI: 10.1109/EWDTS52692.2021.9581036.
27. Baghdadi A. A. A., Hahanov V. I., Litvinova E. I. Methods for analyzing and diagnosing digital devices (analytical review), Automated Control Systems and Automation Devices, 2014, no. 166, pp. 59—74 (in Russian).
28. Aksenova G. P. Necessary and Sufficient Conditions for Design of Completely Checkable Modulo 2 Convolution Circuits, Avtomatika i Telemehanika, 1979, no. 9, pp. 126—135 (in Russian).
29. Sapozhnikov V. V., Sapozhnikov Vl. V. Self-Checking Digital Devices, St. Petersburg, Energoatomizdat, 1992, 224 p. (in Russian).
30. Piestrak S. J. Design of Self-Testing Checkers for Unidirectional Error Detecting Codes, Wroclaw, Oficyna Wydawnicza Politechniki Wroclavskiej, 1995, 111 p.
31. Zakrevskij A., Pottosin Yu., Cheremisinova L. Optimization in Boolean Space, Tallinn, TUT Press, 2009, 241 p.

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