ABSTRACTS OF ARTICLES OF THE JOURNAL "INFORMATION TECHNOLOGIES".
No. 11. Vol. 28. 2022

DOI: 10.17587/it.28.580-589

E. V. Krekhov, Chief Consultant, Assistant Professor,
Almaz-Antey anagement consulting LLC, Russian Technological University, Institute of integrated security and special instrument making, Moscow,
V. E. Krekhov, Head of computing department, I. V. Krekhov, Head of department,
Military Academy the strategic missile forces named after Peter the Great, Branch in Serpukhov

Logic and Circuitry of a Memory Element to Ensure the Reliability Unitary Code and Speed of Ring Counters

Binary encoding of information is prone to errors. The simplest code is a unitary code. Modern coding theory does not allow us to exclude all possible errors in the unitary code. As a result of errors in a bistable memory cell, the unitary code may be corrupted.
The properties and features of simple memory elements based on a bistable cell for computer-aided design in CAD are considered. The logic of the prohibition of indeterminate states of a memory element with negative feedback, in contrast to synchronous and self-synchronous logic, is analyzed. The proposed logic is modeled by blocking combined memory elements on the example of a ring counter. The complexity and speed of the ring counter are analyzed, the reliability of its unitary code is evaluated by the proportion of detected errors.
The purpose of the study is to analyze the circuit complexity and performance of a synchronous-asynchronous memory element with negative feedback and the principle of error prevention in the synchronous-asynchronous mode of complex combined memory elements using the example of a ring counter with an assessment of the reliability of its output equidistant unitary code by the proportion of detected errors.
As a result of the study, using the example of a counter, the possibility of simplifying and improving the performance of digital serial devices with the exception of errors in triggering their discharges, with the exception of those that are not blocked, is shown. The use of forbidding logic to exclude an undefined state of memory during encoding allows the code to be equidistant. The introduction of the prohibition logic into memory is the fact of a sufficient reduction in the number of coding errors. The proposed logic is justified by the simplicity of synchronous-asynchronous memory management. The performance indicators of the developed memory element are comparable to the performance indicators of self-synchronous logic circuits. The logic of a synchronous-asynchronous memory element with negative feedback expands the capabilities of digital devices. The reliability of the unitary code of the proposed ring counter is close to unity. The considered synchronous-asynchronous logic, the possibility of increasing the speed and preventing errors in the memory element will allow choosing more effective ways to develop promising information processing tools using CAD.
Keywords: inhibit logic, memory element error, negative feedback, bistable cell, ring counter, counter performance, reliability of equidistant unitary code

P. 580–589

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