ABSTRACTS OF ARTICLES OF THE JOURNAL "INFORMATION TECHNOLOGIES".
No. 6. Vol. 28. 2022

DOI: 10.17587/it.28.283-293

D. V. Efanov^1,2,3, D. Sc., Associate Professor, IEEE member, D. V. Pivovarov⁴, Ph.D., Senior Lecturer, G. V. Osadchiy³, Ph.D., Deputy General Director — Chief Engineer, M. V. Zueva⁵, Programmer-Analyst,
¹ Peter the Great St. Petersburg Polytechnic University, St. Petersburg,
² Russian University of Transport, Moscow,
³ LLC STC "Complex monitoring systems", St. Petersburg,
⁴ Emperor Alexander I St. Petersburg State Transport University, St. Petersburg,
⁵ LLC "IBS St. Petersburg"

Application of Codes with Low Multiplicity Errors Efficient Detection for the Concurrent Error-Detection Circuit Synthesis by the Boolean Complement Method

The article proposed to synthesize concurrent error-detection circuit (CED) by the Boolean complement method using systematic codes with efficient error detection in the low multiplicity. The classical and modified Hamming's codes using is considered. The code choice features in the CED organization by the Boolean complement method are described. The CED organization structures by the Boolean addition method are given, considering the properties off Hamming code and their modifications. The generalized algorithm implementation for the CED synthesis by the Boolean complement method using Hamming codes and their modifications is formulated. The procedure effectiveness examples for synthesizing the CED according to the proposed methods in comparison with the use of the classical duplication method are given.
Keywords: self-checking digital device; concurrent error-detection circuit (CED circuit); Boolean complement method; code with single- and double error detection; Hamming code; modified Hamming code; ensuring self-verification

Acknowledgements: The presented article was written based on the results of research supported by grant No. MD-2533.2021.4 of the President of the Russian Federation.

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