ABSTRACTS OF ARTICLES OF THE JOURNAL "INFORMATION TECHNOLOGIES".
No. 12. Vol. 24. 2018

DOI: 10.17587/it.24.755-762

A. L. Stempkovskiy, D. Sci., Scientific Director, D. V. Telpukhov, Ph. D., Head of Department, R. A. Solovyev, Ph. D., Chief Researcher, Y. V. Bitkov, Researcher, Institute for Design Problems in Microelectronics (IPPM RAS), Moscow, 124365, Russian Federation, nofrost@inbox.ru,

Development of Methods for Automating Resource-aware Functional ECO Patch Generation

In the modern design process of VLSIs, situations often arise when an incorrect operation of the circuit is detected only at the stage of final verification. Worse, when errors occur even after the final stage of design or production of microcircuits. Correction of errors at such late stages requires enormous labor and financial costs. In order to minimize these costs, methods have been developed for making the changes in the advanced stages of design process (engeneering change order, ECO) for making corrections to the final design, instead of performing a complete redesign. At present, such corrections are mostly made manually, despite the fact that the main CAD vendors already have some automated tools for ECO.
In this paper, we propose methods for automating the functional correction of circuits based on conflicts, as well as methods for analyzing the structure of the circuit. Implemented software demonstrates high efficiency on a number of real-world tasks.
Keywords: engeneering change order, ECO, functional correction, conflicts, ICCAD Contest

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