Exascale Computer Parallel Programming Technology

S. G. Elizarov, Senior Staff Scientist, M.V. Lomonosov Moscow State University, G. A. Lukyanchenko, Postgraduate Student, National Research Centre "Kurchatov Institute", Moscow, V. V. Korneev, Professor, Director for Research, e-mail: korv@rdi-kvant.ru, State Enterprise "Research and Development Institute "Kvant", Moscow

Parallel programming model based on PRAM — Parallel Random Access Model and memory architecture for exascale supercomputer are proposed. Tagged shared memory with additional full/empty bits for each word that keeps the reading from an empty compartment till the data will be written on it is used for preventing memory access conflicts and data synchronization purposes. For native parallel programming we use the 'lightweight threads' approach dividing the program into multiple threads performing relatively short code fragments from a single program with very low overheads. The results are saved in the shared memory. Are described the main programming language features necessary for the offered model.

We present the prototype of FPGA-based exascale supercomputer node made by the model offered above. Node contains more than 1000 cores. Main multiprocessor units including universal cores computing kernels, on-chip communication network, advanced memory controllers etc. are described. Hardware platforms characteristics are provided. Main tests were done on Rosta RC-47 test bench containing four largest Virtex7 FPGAs, eight RLDRAMIII memory channels and PCI Express Gen3 controller. Node prototype was running with Minix3 OS.

The prototype offers a very flexible architecture including control of power and quantity of universal cores and custom computational blocks. User can tune throughput and latency of the memory controllers, communication network and many other blocks of prototype for it's particular tasks. So the exascale supercomputer node prototype offers the possibility of supercomputer's speed growth experimental research using such perspective approaches like a lightweight threads and tagged shared memory.

Keywords: exascale supercomputer, shared memory parallel programming model, multicore processor on FPGA

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