The Fault-tolerant Computer Design Techniques Using Triple Modular Redundancy (2oo3) Architecture

S. A. Bukashkin , B. N. Krivoshein , e-mail: Boris.Krivoshein@lanit-tercom.com, A. N. Terekhov , e-mail: Andrey.Terekhov@lanit-tercom.com, N. F. Fominykh

This article contains an overview of the fault-tolerant redundant systems design techniques with an example of the original computer OVK based on the TMR (2oo3) hardware architecture. The overview includes examples of the functional safety estimation, failure rate calculations, solving of general issues related to the fault-tolerant systems design. The theoretical approaches are confirmed by practical samples of algorithms, protocols and other engineering solutions used for OVK design and implementation

Keywords: fault-tolerant computer, voting, triple modular redundancy, TMR, architecture 2oo3, functional safety, reliability

pp. 12–20