DOI: 10.17587/prin.9.291-304

Verification of VHDL Descriptions Networks of Synchronous Finite State Machines

N. A. Avdeev, avdeev_n@newman.bas-net.by, P. N. Bibilo, bibilo@newman.bas-net.by, The United Institute of Informatics Problems of the National Academy of Sciences of Belarus, Minsk, 220012, Belarus, V. V. Korobkin, vvk@niimvs.ru, Acad. Kalyaev Scientific Research Institute of Multiprocessor Computer Systems, Taganrog, 347928, Russian Federation, A. E. Kolodenkova, anna82_42@mail.ru, Samara State Technical University, Samara, 443100, Russian Federation

Corresponding author: Bibilo Petr N., Head of Laboratory, The United Institute of Informatics Problems of the National Academy of Sciences of Belarus, 220012, Minsk, Belarus, E-mail: bibilo@newman.bas-net.by

Finite state machines are widely applied in the development of digital systems for description of control logic nodes, microprocessors, interface circuits and so on. This work proposes verification procedure of VHDL description of parallel arrays of finite state machines in Questa Sim simulation system. The main advantage of Questa Sim is that the model of finite state machine (FSM) can be verified if it is written according to certain template. Verification is comprised of validating for compliance of VHDL description of finite state machine array with design specifications. The method utilizes the capabilities of the Questa Sim system, which makes it possible to identify the oriented graphs of the transitions of the component machines and to calculate the number of the arc passings in the graphs based on the results of simulation. However, the Questa Sim system does not recognize the FSM network and does not have the means to construct the tests based on the simulation results. Therefore, to solve these problems, it is suggested to store the simulation results — the sequence of input sets (stimuli) and the state tuples of the component machines, and to check the execution of transitions in the state graph of the machine network based on the sequences obtained,and, thus, to conduct the verification. In addition, this article discusses an example of description of FSMs and FSM arrays using VHDL.

Keywords: digital systems, VHDL descriptions, verification, simulation, finite state machines

pp. 291–304

For citation:
Avdeev N. A., Bibilo P. N., Korobkin V. V., Kolodenkova A. E. Verification of VHDL Descriptions Networks of Synchronous Finite State Machines, Programmnaya Ingeneria, 2018, vol. 9, no. 7, pp. 291—304.