A programmable logic device (PLD) is an electronic component that is used to build digital circuits that are reprogrammable. PLD is widely used in different implementations of information protection facilities. It offers high operating speed and possibility to quickly change compromised or obsolete encryption algorithms due to flexibility of programmatic methods and power of hardware implementations, such as ASIC. This paper deals with a hardware implementation of ZUC cipher. This implementation can be implemented by using logical conjunction, disjunction, negation and delay blocks. The main indicator of productivity of such implementations is a circuit depth, namely the maximum length of a simple way of the circuit (negation elements are not taken into account). ZUC is a stream cipher designed by the Data Assurance and Communication Security Research Center (DACAS) of the Chinese Academy of Sciences. The cipher forms the core of the 3GPP mobile standards 128-EEA3 (for encryption) and 128-EIA3 (for message integrity). It was proposed for inclusion in the Long Term Evolution (LTE) or the 4th generation of cellular wireless standards (4G). A detailed description of ZUC cipher is provided at the beginning of the article. The depth estimation of basic components (Adder, S-box, etc.) and the simplest cipher implementation are presented. The article concludes with several optimizing circuit transformations and statements which contribute to reduction of implementation depth. The article also includes the review of existing studies.