DOI: 10.17587/prin.9.156-162

Asymmetric Marker Processing

M. V. Baklanovsky, m.baklanovsky@spbu.ru, B. N. Krivoshein, bnkv@outlook.com, A. N. Terekhov, a.terekhov@spbu.ru, M. A. Terekhov, st054464@student.spbu.ru, Saint Petersburg State University, Saint Petersburg, 199034, Russian Federation, A. E. Sibiryakov, a.sibiryakov@urfu.ru, Ural Federal University named after the first President of Russia B. N. Yeltsin, Ekaterinburg, 620002, Russian Federation

Corresponding author: Terekhov Andrey N., Professor, Saint Petersburg State University, 199034, Saint Petersburg, Russian Federation, E-mail: a.terekhov@spbu.ru

An approach is proposed to create heterogeneous computing systems with the capabilities of organizing a single computing environment with a unified mechanism for transferring control, a through design route, automatic generation of a part of the system elements in the compilation process, and with debugging at the system level. All stack protocols, implementation on shared memory and work with FPGA are described. The results of speed tests of the authors implementation are given. The approach can be used for elements of hardware protection against reverse analysis, for creating high-performance systems with specialized computing cores and partial parallelism and for improving fault tolerance.

Keywords: processor, control transfer, protocol stack, reliability, performance, security, fault tolerance

pp. 156–162

For citation:
Baklanovsky M. V., Krivoshein B. N., Terekhov A. N., Terekhov M. A., Sibiryakov A. E. Asymmetric Marker Processing, Programmnaya Ingeneria, 2018, vol. 9, no. 4, pp. 156—162.