Journal "Software Engineering"
a journal on theoretical and applied science and technology
Issue N1 2017 year
We propose to conduct an estimation of power consumption of finite state machines represented by logic circuits. We use structural and behavior VHDL-models of these circuits. Our approach to power consumption estimation of synchronous logic circuits of finite state machines is based on the implementation of extended functional VHDL-models of CMOS elements and fast tools of logical VHDL-simulation. An extended functional VHDL-model contains not only functions of its description but states which take into account variations of power consumption of inputs and outputs of elements. The technique of upper limitation of power consumption of logic circuits concludes in the process of looking for tests which induce reducing of power consumption — energy-intensive tests. We propose an algorithm for energy-intensive tests generation which uses cycle-accurate sequences: a set of tests T flows through S-state of a finite state machine; values of power consumption E of a logic circuit of a finite state machine. A common idea of the algorithm concludes in the process of finding a loop L into S (path in a graph of transitions of automaton). This loop is characterized with the maximum in a set of average values. On the last step of the algorithm is in the finding a path from an initial state to a vertex from the found loop. A set of tests from L occur m-fold in the resulting energy-intensive test Te, where m can vary. The experiments on VHDL benchmarks of finite states machines have shown that the proposed technique implementation of energy-intensive tests leads to 40 % increasing of power consumption for structural VHDL-models for the found tests. Generating energy-intensive tests allows us to test of digital blocks for operability in the high power consumption mode.