DOI: 10.17587/prin.15.570-577
Application of UVM Methodology to Modeling Precision Digital Signal Processing Devices
I. E. Tarasov, Head of Laboratory of Specialized Computing Systems, ilya_e_tarasov@mail.ru,
RTU MIREA, Moscow, 119454, Russian Federation
Corresponding author: Ilya E. Tarasov, Head of Laboratory of Specialized Computing Systems, RTU MIREA, Moscow, 119454, Russian Federation E-mail: ilya_e_tarasov@mail.ru
Received on August 02, 2024
Accepted on September 10, 2024
The purpose of the article is to analyze the Universal Verification Methodology (UVM) approach and develop its modification for modeling precision digital signal processing devices as part of periodic signal phase meters. The article proposes a partial implementation of UVM techniques and methods based on general-purpose programming languages, which is distinguished by the presence of a subsystem for metrological evaluation of the characteristics of the simulated measuring device, while the UVM approach, implemented in the Accelera class library in the System Verilog language, assumes the presence of a reference response with which comparison is made. Thus, the proposed approach, while preserving the methodological basis of UVM, allows modifying it for use in systems where the reference response is not assumed, since it is the subject of the study.
Keywords: modelling, measurement, phase, wavelet analysis, digital signal processing
pp. 570—577
For citation:
Tarasov I. E. Application of UVM Methodology to Modeling Precision Digital Signal Processing Devices, Programmnaya Ingeneria, 2024, vol. 15, no. 10, pp. 570—577. DOI: 10.17587/prin.15.570-577. (in Russian).
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