DOI: 10.17587/prin.14.377-387

Synthesis of Modular Multipliers

P. N. Bibilo, bibilo@newman.bas-net.by The United Institute of Informatics Problems of the National Academy of Sciences of Belarus, Minsk, 220012, Belarus

Corresponding author: Bibilo Petr N., Head of Laboratory, The United Institute of Informatics Problems of the National Academy of Sciences of Belarus, Minsk, 220012, Belarus, E-mail: petr.olibib@yandex.ru; bibilo@newman.bas-net.by

The results of experiments on the circuit implementation of modular multipliers in the design library of ASIC (Application-Specific Integrated Circuits) and FPGA (Field-Programmable Gate Array) are presented. The initial descriptions of modular multiplier projects were given by systems of not fully defined (partial) Boolean functions and algorithmic VHDL descriptions. Logical optimization was carried out in the class of disjunctive normal forms (DNF) and representations of Boolean function systems by BDD (Binary Decision Diagrams). The synthesized circuits were evaluated by area and time delay. It is established that the use of partial Boolean function models and preliminary logi­cal BDD optimization allows one to improve the parameters of synthesized ASIC and FPGA blocks for small module values, however, the best solutions for large module values can be obtained using algorithmic VHDL descriptions of modular multipliers. In the synthesis of modular multiplier circuits as part of an FPGA and the use of ISE and Vivado design systems it is advisable to use synthesized VHDL operations (a*b) mod p.

Keywords: modular calculations, modular multiplier, integer division operation, system of Boolean functions, Disjunctive Normal Form, Binary Decision Diagram, Shannon expansion, digital logic synthesis, VHDL, ASIC, FPGA

pp. 377–387

For citation:
Bibilo P. N. Synthesis of Modular Multipliers, Programmnaya Ingeneria, 2023, vol. 14, no. 8, pp. 377—387. DOI: 10.17587/prin.14.377-387 (in Russian).

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