Journal "Software Engineering"
a journal on theoretical and applied science and technology
ISSN 2220-3397

Issue N4 2023 year

DOI: 10.17587/prin.14.175-186
Efficiency Analysis of Concurrent Error-Detection Circuits on the Basis of Assessment by Belonging of Calculated Functions to Self-Dual Class and Preliminary Compression of Signals Using Linear Codes
D. V. Efanov1,2,3 D. Sc. (Engineering), Associate Professor, Professor, TrES-4b@yandex.ru, T. S. Pogodina2, Student, pogodina-ts@mail.ru
1 Peter the Great St. Petersburg Polytechnic University, St. Petersburg, 195251, Russian Federation
2 Russian University of Transport, Moscow, 127994, Russian Federation
3 LLC Research and Design Institute for Transport and Construction Safety, St. Petersburg, 192102, Russian Federation
Corresponding author: Dmitry V. Efanov, D. Sc. (Engineering), Associate Professor, Professor, Peter the Great St. Petersburg Polytechnic University, St. Petersburg, 195251, Russian Federation, Russian University of Transport, Moscow, 127994, Russian Federation, LLC Research and Design Institute for Transport and Construction Safety, St. Petersburg, 192102, Russian Federation, E-mail: TrES-4b@yandex.ru
Received on January 20, 2023
Accepted on February 15, 2023

A method is described for checking of calculations on whether functions belong to the class of self-dual with using well-known linear codes for preliminary compression of signals from the outputs of combinational devices in order to reduce the number of controlled signals. A generalized structure for organizing the checking of calculations with signal compression using arbitrary separable codes is proposed, which complements the well-known structures of self-dual check of parity calculations («self-dual parity») and self-dual check with duplication of each function («self-dual duplication))). In the concurrent error-detection circuit according to the presented method, all devices, except for the self-dual complement block, are standardized (typical). Therefore, to synthesize the concurrent error-detection circuit, it is necessary to obtain only the structure of this block in the selected elemental basis. The article presents a technique for synthesizing a block of self-dual complement when organizing the checking of calculations using arbitrary separable codes. Examples of the implementation of devices with concurrent error-detection circuits based on well-known linear codes — parity codes, Hamming codes and their modifications are given. Some results of mod­eling devices with concurrent error-detection circuits are given, noting the advantages and disadvantages of using each of the codes considered. The results obtained in the study can be applied in the development of self-checking computing devices and systems.

Keywords: combinational device; checking of calculations; checking self-duality of functions; parity code; Hamming code; modified Hamming code; self-checking device; temporal redundancy; self-dual complement
pp. 175–186
For citation:
Efanov D. V., Pogodina T. S. Efficiency Analysis of Concurrent Error-Detection Circuits on the Basis of Assessment by Belonging of Calculated Functions to Self-Dual Class and Preliminary Compression of Signals Using Linear Codes, Programmnaya Ingeneria, 2023, vol. 14, no. 4, pp. 175—186. DOI: 10.17587/prin.14.175-186 (in Russian) .
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