DOI: 10.17587/prin.13.259-271

Parallelism Reduction Methods in the High-Level VLSI Synthesis Implementation

D. S. Romanova, daryaooo@mail.ru, Siberian Federal University, Krasnoyarsk, 660041, Russian Federation, Krasnoyarsk State Agrarian University, Krasnoyarsk, 660049, Russian Federation, O. V. Nepomnyashchiy, Siberian Federal University, Krasnoyarsk, 660041, Russian Federation, A. I. Legalov, legalov@mail.ru, National Research University — Higher School of Economics, Moscow, 101000, Russian Federation, I. N. Ryzhenko, rodgi.krs@gmail.com, N. Y. Sirotinina, nsirotinina@sfu-kras.ru, Siberian Federal University, Krasnoyarsk, 660041, Russian Federation

Corresponding author: Romanova Darya S., Postgraduate Student, Krasnoyarsk State Agrarian University, Krasnoyarsk, 660049, Russian Federation, E-mail: daryaooo@mail.ru

The problems and solutions in the field of ensuring architectural independence and implementation of digital integrated circuits end-to-end design processes are considered. The paper focuses on the need to find a solution to the problem of program portability during the development of integrated circuits. A review of the main software and tools used to design digital circuits (Verilog, System-C, Handel-C, Lava, Hydra, Wired, COLAMO, Chisel and etc.) is presented. The method and language of parallel programming for functional flow synthesis of design solutions PIFAGOR is presented. The example of the source and generated code in the PIFAGOR and Verilog languages is given. During the method implementation, the tasks of reducing parallelism and estimating the occupied resources were highlighted. The main feature of the developed method is the introduction of the additional layer (HDL graph) into the synthesis process. Algorithms for the parallelism reduction have been developed. This method is demonstrated on the example of parallelism reduction while going to the FPGA platform solving the problem of calculating a 4-point FFT (Fast Fourier Transform). As part of the solution of this task, an assessment of memory resources and an assessment of computing resources were carried out. The results of software tools development for design support including the parallelism reduction preprocessor and resource estimation preprocessor and practical VLSI projects are presented.

Keywords: integrated circuit, parallel computing model, algorithm, program, high-level synthesis, functional-stream language

pp. 259—271

For citation:
Romanova D. S., Nepomnyashchiy O. V., Legalov A. I., Ryzhenko I. N., Sirotinina N. Y. Parallelism Reduction Methods in the High-Level VLSI Synthesis Implementation, Programmnaya Ingeneria, 2022, vol. 13, no. 6, pp. 259—271.

The article is based on the materials of the report at the Seventh International Conference "Actual problems of Systems and Software Engineering" APSSE 2021