The article considers high-level design flow of single-chip systems for parallel data processing. The authors present solution on the base of the original functional data-flow language and the model of massive parallel processing. The language is used for description of the initial algorithm. The solution provides architectural independence of the program and allows to consider a wide variety of solutions taking constraints into account, and to select the optimal solution. The developed software toolkit for high-level design is described. The toolkit allows a developer to translate, debug, optimize programs and convert algorithm descriptions from the functional data stream language to a hardware description language. The developed software has been successfully tested on a number of test cases.