A comparative analysis of computing device architectures, including those of a processor type, is given for organizing mass-parallel computing with an assessment of performance, efficient use of VLSI chip area and power consumption. Several architectures of computing devices intended for the implementation of parallel computing, including both non-programmable and programmable devices, are considered. The analysis shows that the considered architectures have a number of features that limit their use in problem-oriented VLSI, such as limited functionality, increased power consumption, inefficient use of the chip area, inefficient use of computing nodes in the process of algorithms. The process of designing problem-oriented VLSI should be performed using complex optimization according to the parameters determined at various design stages — from the choice of architecture to the topological implementation of VLSI. An approach to increase the productivity of development of problem-oriented VLSI based on the co-optimization of software and hardware components of the system with the requirements that are formed by reducing the design standards to 28 nm is presented. The approach is based on the use of system modeling, using both VLSI emulation at the level of the program model, and modeling at the register transfer level, with the parameters used to assess the quality of the project with respect to the selected optimality criteria. The use of system modeling with a preliminary assessment of the achievable characteristics of the hardware platform (area, clock frequency, power consumption) allows one to get a set of architecture options, including the number of nodes, memory size, instruction set, ALU structure. This approach is the basis for the development of appropriate modules or parameterization of ready-made solutions.